MC68340AB16E Datasheet, PDF (419/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
11.8 DMA MODULE AC ELECTRICAL SPECIFICATIONS (See notes (a), (b), (c), and
(d) corresponding to part operation, GND = 0 Vdc, TA = 0 to 70°C; see Figure 11-12)
3.3 V 3.3 V or 5.0 V 5.0 V
8.39 MHz 16.78 MHz 25.16 MHz
Num.
Characteristic
Min Max Min Max Min Max Unit
1 CLKOUT Low to AS, DACK, DONE Asserted
— 60 — 30 — 20 ns
2 CLKOUT Low to AS, DACK Negated
— 60 — 30 — 20 ns
3 DREQ≈ Asserted to AS Asserted (for DMA Bus
3t _cyc + tAIST + tCLSA
ns
Cycle)
4¹ Asynchronous Input Setup Time to CLKOUT
Low
15 — 8, 5 —
5
—
ns
5 Asynchronous Input Hold Time from CLKOUT 30 — 15 — 10 —
ns
Low
6 AS to DACK Assertion Skew
-30 30 –15 15 –10 10 ns
7 DACK to DONE Assertion Skew
-30 30 –15 15 –8 8
ns
8 AS, DACK, DONE Width Asserted
200 — 100 — 70 —
ns
8A AS, DACK, DONE Width Asserted (Fast
Termination Cycle)
80 — 40 — 28 —
ns
NOTES:
(a) The electrical specifications in this document for both the 8.39 and 16.78 MHz @ 3.3 V ±0.3 V are preliminary
and apply only to the appropriate MC68340V low voltage part.
(b) The 16.78-MHz specifications apply to the MC68340 @ 5.0 V ±5% operation.
(c) The 25.16 MHz @ 5.0 V ±5% electrical specifications are preliminary.
(d) For extended temperature parts T _A = –40 to +85°C. These specifications are preliminary.
1. Specification #4 for 16.78 MHz @ 3.3 V ±0.3 V will be 8 ns.
CPU_CYCLE
(DMA REQUEST)
DMA_CYCLE
S0
S1
S2
S3
S4
S5
S0
S1
S2
S3
S4
S5
CLKOUT
4
DONE (INPUT)
DREQ
AS
5
3
1
6
8
DACK
1
2
DONE
(OUTPUT)
7
1
Figure 11-12. DMA Signal Timing Diagram
MOTOROLA
MC68340 USER’S MANUAL
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11-19