MC68340AB16E Datasheet, PDF (274/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
MCR1, MCR2
15
14
13
12
11
STP FRZ1 FRZ0 SE
0
RESET:
0
0
0
0
0
10
9
ISM
0
0
8
7
6
5
4
SUPV
MAID
0
1
0
0
0
$780, $7A0
3
2
1
0
IARB
0
0
0
0
Supervisor Only
STP—Stop Bit
1 = Setting the STP bit stops all clocks within the DMA module except for the clock
from the IMB. The clock from the IMB remains active to allow the CPU32 access
to the MCR. The clock stops on the low phase of the clock and remains stopped
until the STP bit is cleared by the CPU32 or a hardware reset. Accesses to DMA
module registers while in stop mode produce a bus error. The DMA module
should be disabled in a known state before setting the STP bit. The STP bit
should be set prior to executing the LPSTOP instruction to reduce overall power
consumption.
0 = The channel operates in normal mode.
NOTE
The DMA module uses only one STP bit for both channels. A
read or write to either MCR accesses the same STP control bit.
FRZ1, FRZ0—Freeze
These bits determine the action taken when the FREEZE signal is asserted on the IMB
when the CPU32 has entered background debug mode. The DMA module negates BR
and keeps it negated until FREEZE is negated or reset. Table 6-1 lists the action taken
for each bit combination.
Table 6-1. FRZx Control Bits
FRZ1
0
0
FRZ0
0
1
Action
Ignore FREEZE
Reserved
1
0
Freeze on Boundary*
1
1
Reserved
*The boundary is defined as any bus cycle by
the DMA module.
NOTE
The DMA module uses only one set of FRZx bits for both
channels. A read or write to either MCR accesses the same
FRZx control bits.
6-24
MC68340 USER’S MANUAL
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