MC68340AB16E Datasheet, PDF (279/441 Pages) Motorola, Inc – Integrated Processor with DMA User’s Manual

Freescale Semiconductor, Inc.
DSIZE—Destination Size Control Field
This field controls the size of the destination (write) bus cycle that the DMA channel is
running. Table 6-3 defines these bits.
Table 6-3. DSIZEx Encoding
Bit 7
0
Bit 6
0
Definition
Long Word*
0
1
1
0
1
1
Byte
Word
Not Used
*External logic is required to complete a long-
word transfer.
REQ—Request Generation Field
This field controls the mode of operation the DMA channel uses to make an operand
transfer request. Table 6-4 defines these bits.
Bit 5
0
0
1
1
Table 6-4. REQx Encoding
Bit 4
0
1
0
1
Definition
Internal Request at Programmable Rate
Reserved
External Request Burst Transfer Mode
External Request Cycle Steal
BB—Bus Bandwidth Field
This field controls the percentage of 1024 clock periods of the IMB that the DMA
channel can use during internal requests only. Table 6-5 defines these bits.
Table 6-5. BBx Encoding and Bus Bandwidth
REQ Field
Bit 5 Bit 4
0
0
0
0
0
0
0
0
BB Field
Bit 3 Bit 2
0
0
0
1
1
0
1
1
Definition
25%
50%
75%
100%
Bus Bandwidth
(Clock Periods)
256
512
768
1024
MOTOROLA
MC68340 USER’S MANUAL
6-29
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