LAN9117 Datasheet, PDF (99/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
6.4 RX Data FIFO Direct PIO Reads
In this mode the upper address inputs are not decoded, and any read of the LAN9117 will read the RX Data FIFO. This
mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting the
FIFO_SEL signal to high-order address line. This mode is useful when the host processor must increment its address
when accessing the LAN9117. Timing is identical to a PIO read, and the FIFO_SEL signal has the same timing charac-
teristics as the address lines.
Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
FIGURE 6-3:
RX DATA FIFO DIRECT PIO READ CYCLE TIMING
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
Note: The “Data Bus” width is 16 bits.
TABLE 6-5:
Symbol
t_cycle
t_csl
t_csh
t_csdv
t_asu
t_ah
t_don
t_doff
t_doh
RX DATA FIFO DIRECT PIO READ TIMING
Description
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address, FIFO_SEL Setup to nCS, nRD Valid
Address, FIFO_SEL Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
MIN
TYP
MAX Units
45
ns
32
ns
13
ns
30
ns
0
ns
0
ns
0
ns
7
ns
0
ns
Note: An RX Data FIFO Direct PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends
when either or both nCS and nRD are de-asserted. They may be asserted and de-asserted in any order.
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DS00002267A-page 99