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LAN9117 Datasheet, PDF (96/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER
LAN9117
TABLE 6-1: READ AFTER WRITE TIMING RULES
Register Name
Minimum Wait Time for Read Following
Any Write Cycle
(in ns)
ID_REV
0
IRQ_CFG
135
INT_STS
90
INT_EN
45
BYTE_TEST
0
FIFO_INT
45
RX_CFG
45
TX_CFG
45
HW_CFG
45
RX_DP_CTRL
45
RX_FIFO_INF
0
TX_FIFO_INF
135
PMT_CTRL
315
GPIO_CFG
45
GPT_CFG
45
GPT_CNT
135
WORD_SWAP
45
FREE_RUN
180
RX_DROP
0
MAC_CSR_CMD
45
MAC_CSR_DATA
45
AFC_CFG
45
E2P_CMD
45
E2P_DATA
45
Number of BYTE_TEST Reads
(Assuming Tcycle of 45ns)
0
3
2
1
0
1
1
1
1
1
0
3
7
1
1
3
1
4
0
1
1
1
1
1
6.1.2 SPECIAL RESTRICTIONS ON BACK-TO-BACK READ CYCLES
There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific regis-
ters after reading resources that have side effects. In many cases there is a delay between reading the LAN9117, and
the subsequent indication of the expected change in the control register values.
In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have been estab-
lished. These periods are specified in Table 6-2, "Read After Read Timing Rules". The host processor is required to wait
the specified period of time between read operations of specific combinations of resources. The wait period is depen-
dent upon the combination of registers being read.
Performing "dummy" reads of the BYTE_TEST register is a convenient way to ensure that the minimum wait time restric-
tion is met. Table 6-2 also shows the number of dummy reads that are required for back-to-back read operations. The
number of BYTE_TEST reads in this table is based on the minimum timing for Tcycle (45ns). For microprocessors with
slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time spec-
ified in the table. Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.
DS00002267A-page 96
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