LAN9117 Datasheet, PDF (25/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
Note: The EEPROM device powers-up in the erase/write disabled state. To modify the contents of the EEPROM
the host must first issue the EWEN command.
If an operation is attempted, and an EEPROM device does not respond within 30mS, the LAN9117 will timeout, and the
EPC timeout bit (EPC_TO) in the E2P_CMD register will be set.
Figure 3-3, "EEPROM Access Flow Diagram" illustrates the host accesses required to perform an EEPROM Read or
Write operation.
FIGURE 3-3:
EEPROM ACCESS FLOW DIAGRAM
EEPROM Write
EEPROM Read
Idle
Idle
Write Data
Regis ter
W r ite
Command
Regis ter
Busy Bit = 0
Read
Command
Regis ter
Write
Command
Re gis te r
Read
Command
Re gis te r
Busy Bit = 0
Read Data
Re gis te r
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is disabled, the EEDIO
and ECLK signals can be used as general-purpose outputs, or they may be used to monitor internal MII signals.
3.9.2.1 Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the E2P_CMD register. The
operations are commonly supported by “93C46” EEPROM devices. A description and functional timing diagram is pro-
vided below for each operation. Please refer to the E2P_CMD register description in Section 5.3.23, "E2P_CMD –
EEPROM Command Register," on page 77 for E2P_CMD field settings for each command.
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