LAN9117 Datasheet, PDF (77/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
TABLE 5-5: BACKPRESSURE DURATION BIT MAPPING
Backpressure Duration
[19:16]
0h
1h
2h
3h
4h
5h
6h
100Mbs Mode
5uS
10uS
15uS
25uS
50uS
100uS
150uS
10Mbs Mode
7.2uS
12.2uS
17.2uS
27.2uS
52.2uS
102.2uS
152.2uS
7h
200uS
8h
250uS
9h
300uS
Ah
350uS
Bh
400uS
Ch
450uS
Dh
500uS
Eh
550uS
Fh
600uS
202.2uS
252.2uS
302.2uS
352.2uS
402.2uS
452.2uS
502.2uS
552.2uS
602.2uS
5.3.23 E2P_CMD – EEPROM COMMAND REGISTER
Offset:
B0h
Size:
32 bits
This register is used to control the read and write operations with the Serial EEPROM.
Bits
Description
31 EPC Busy: When a 1 is written into this bit, the operation specified in the
EPC command field is performed at the specified EEPROM address. This
bit will remain set until the operation is complete. In the case of a read this
means that the host can read valid data from the E2P data register. The
E2P_CMD and E2P_DATA registers should not be modified until this bit is
cleared. In the case where a write is attempted and an EEPROM is not
present, the EPC Busy remains busy until the EPC Time-out occurs. At that
time the busy bit is cleared.
Note:
EPC busy will be high immediately following power-up or reset.
After the EEPROM controller has finished reading (or attempting
to read) the MAC address from the EEPROM the EPC Busy bit is
cleared.
Type
SC
Default
0
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