LAN9117 Datasheet, PDF (33/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
• Soft Reset (SRST)
• PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)
• PHY Soft Reset via PHY Basic Control Register (PHY REG 0.15)
Table 3-10 shows the effect of the various reset sources on the LAN9117's circuitry.
TABLE 3-10: RESET SOURCES AND AFFECTED CIRCUITRY
Reset Source
HBI
PLL Note
3-13
NASR
Registers
Note 3-13
MIL
MAC
PHY
Note 3-11
POR X
X
X
X
X
X
nRESET X
X
X
X
X
X
SRST
X
X
X
PHY_RST
X
PHY REG 0.15
X
EEPROM MAC
ADDR. Reload
Note 3-12
X
X
X
Config.
Straps
Latched
X
X
Note 3-11
Note 3-12
Note 3-13
After any PHY reset, the application must wait until the “Link Status” bit in the PHY’s “Basic Status
Register” (PHY Reg. 1.2) is set before attempting to transmit or receive data.
After a POR, nRESET or SRST, the LAN9117 will automatically check for the presence of an external
EEPROM. After any of these resets the application must verify that the EPC Busy Bit (E2P_CMD, bit
31) is cleared before attempting to access the EEPROM, or change the function of the GPO/GPIO
signals, or before modifying the ADDRH or ADDRL registers in the MAC.
HBI - “Host Bus Interface”, NASR - Not affected by software reset.
3.11.1 POWER-ON RESET (POR)
A Power-On reset occurs whenever power is initially applied to the LAN9117, or if power is removed and reapplied to
the LAN9117. A timer within the LAN9117 will assert the internal reset for approximately 22ms. The READY bit in the
PMT_CTRL register can be read from the host interface and will read back a ‘0’ until the POR is complete. Upon com-
pletion of the POR, the READY bit in PMT_CTRL is set high, and the LAN9117 can be configured via its control regis-
ters.
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) after an internal
reset (22ms). If the software driver polls this bit and it is not set within 100ms, then an error
condition occurred.
3.11.2 HARDWARE RESET INPUT (NRESET)
A hardware reset will occur when the nRESET input signal is driven low. The READY bit in the PMT_CTRL register can
be read from the host interface, and will read back a ‘0’ until the hardware reset is complete. Upon completion of the
hardware reset, the READY bit in PMT_CTRL is set high.
After the “READY” bit is set, the LAN9117 can be configured via its control registers. The nRESET signal is pulled-high
internally by the LAN9117 and can be left unconnected if unused. If used, nRESET must be driven low for a minimum
period as defined in Section 6.8, "Reset Timing," on page 103.
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) immediately. If
the software driver polls this bit and it is not set within 100ms, then an error condition
occurred.
3.11.3 RESUME RESET TIMING
After issuing a write to the BYTE_TEST register to wake the LAN9117 from a power-down state, the READY bit in
PMT_CTRL will assert (set High) within 2ms.
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) within 2 ms. If
the software driver polls this bit and it is not set within 100ms, then an error condition
occurred.
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DS00002267A-page 33