LAN9117 Datasheet, PDF (38/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
FIGURE 3-13:
SIMPLIFIED HOST TX FLOW DIAGRAM
init
Last Buffer in
Packet
Idle
Check
available
FIFO
space
TX Status
Available
Read TX
Status
(optional)
Write
TX
Command
Write
Start
Padding
(optional)
Write
Buffer
Not Last Buffer
3.13.1 TX BUFFER FORMAT
TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the TX data buffer
before moving the Ethernet packet data. The TX command A and command B are 32-bit values that are used by the
LAN9117 in the handling and processing of the associated Ethernet packet data buffer. Buffer alignment, segmentation
and other packet processing parameters are included in the command structure. The following diagram illustrates the
buffer format.
DS00002267A-page 38
 2005-2016 Microchip Technology Inc.