LAN9117 Datasheet, PDF (102/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
6.7 TX Data FIFO Direct PIO Writes
In this mode the upper address inputs are not decoded, and any write to the LAN9117 will write the TX Data FIFO. This
mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the
FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address
when accessing the LAN9117. Timing is identical to a PIO write, and the FIFO_SEL signal has the same timing charac-
teristics as the address lines.
FIGURE 6-7:
TX DATA FIFO DIRECT PIO WRITE TIMING
FIFO_SEL
A[2:1]
nCS, nWR
Data Bus
Note: The “Data Bus” width is 16 bits.
TABLE 6-7:
Symbol
t_cycle
t_csl
t_csh
t_asu
t_ah
t_dsu
t_dh
TX DATA FIFO DIRECT PIO WRITE TIMING
Description
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
MIN
TYP
MAX Units
45
ns
32
ns
13
ns
0
ns
0
ns
7
ns
0
ns
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends
when either or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
DS00002267A-page 102
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