LAN9117 Datasheet, PDF (58/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
5.0 REGISTER DESCRIPTION
The following section describes all LAN9117 registers and data ports.
Note 5-1
The LAN9117 host bus interface supports 16-bit bus transfers; internally, all data paths are 32-bits
wide. Figure 5-1 describes the memory map with respect to pairs of atomic 16-bit transactions.
FIGURE 5-1:
LAN9117 MEMORY MAP
FCh
RESERVED
B4h
EEPROMPort
B0h
ACh
A8h
MACCSRPort
A4h
A0h
50h
4Ch
TX Status FIFO PEEK
48h
TX Status FIFO Port
44h
RX Status FIFO PEEK
40h
RX Status FIFO Port
3Ch
TX Data FIFO Alias Ports
24h
20h
TX Data FIFO Port
1Ch
RX Data FIFO Alias Ports
04h
Base + 00h
RX Data FIFO Port
DS00002267A-page 58
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