LAN9117 Datasheet, PDF (35/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
• The LAN9117 Receiver must be halted.
• The halting of the LAN9117 receiver must be complete.
• The PHY_CLK_SEL field must be set to 10b. This action will disable the MII clocks to the LAN9117 internal logic
for both the internal PHY, and the external MII interface.
• The host must wait a period of time not less than 5 cycles of the slowest operating clock before executing the next
step in this procedure.
APPLICATION NOTE: For example, if the internal PHY was operating in 10Mbs mode, and the external PHY was
operating at 100Mbs mode, the internal PHY’s TX_CLK and RX_CLK period is the longest,
and will determine the required wait-time. In this case the TX_CLK and RX_CLK period for
the internal PHY is 400ns, therefore the host must wait 2us (5*400ns) before proceeding. If
the clocks of the device being deselected by the switch are not running, they are not
considered in this calculation.
• Set EXT_PHY_SEL described in Section 5.3.9, "HW_CFG—Hardware Configuration Register" to the desired MII
port. This step switches the RXD[3:0], RX_DV, RX_ER, TXD[3:0], TX_EN, CRS and COL signals to the desired
port.
• Set PHY_CLK_SEL described in Section 5.3.9, "HW_CFG—Hardware Configuration Register" to the desired port.
This must be the same port that is selected by EXT_PHY_SEL.
• The host must wait a period of time of not less than 5 cycles of the slowest, newly enabled clock before executing
the next step in this procedure.
• Enable theLAN9117 transmitter.
• Enable the LAN9117 receiver.
The process is complete. The LAN9117 is now operational using the newly selected MII device.
The above procedure must be repeated each time the MII port is switched. The procedure is identical when switching
from internal PHY to external MII, or vice-versa.
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DS00002267A-page 35