LAN9117 Datasheet, PDF (53/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
4.2.3 NRZI AND MLT3 ENCODING
The scrambler block passes the 5-bit wide parallel data to the NRZI converter where it becomes a serial 125MHz NRZI
data stream. The NRZI is encoded to MLT-3. MLT3 is a tri-level code where a change in the logic level represents a code
bit “1” and the logic output remaining at the same level represents a code bit “0”.
4.2.4 100M TRANSMIT DRIVER
The MLT3 data is then passed to the analog transmitter, which launches the differential MLT-3 signal, on outputs TXP
and TXN, to the twisted pair media via a 1:1 ratio isolation transformer. The 10Base-T and 100Base-TX signals pass
through the same transformer so that common “magnetics” can be used for both. The transmitter drives into the 100
impedance of the CAT-5 cable. Cable termination and impedance matching require external components.
4.2.5 100M PHASE LOCK LOOP (PLL)
The 100M PLL locks onto reference clock and generates the 125MHz clock used to drive the 125 MHz logic and the
100Base-Tx Transmitter.
FIGURE 4-2:
RECEIVE DATA PATH
MAC
RX_CLK
100M
PLL
Internal
MII 25MHz by 4 bits
MII
NRZI
MLT-3
Converter ^{NRZI Converter}
25MHz
by 4 bits
4B/5B 25MHz by Descrambler
Decoder
5 bits
and SIPO
125 Mbps Serial
MLT-3
DSP: Timing
recovery, Equalizer
and BLW Correction
A/D
Converter
MLT-3
Magnetics
MLT-3
RJ45
MLT-3 CAT-5
6 bit Data
4.3 100Base-TX Receive
The receive data path is shown in Figure 4-2. Detailed descriptions are given below.
4.3.1 100M RECEIVE INPUT
The MLT-3 from the cable is fed into the PHY (on inputs RXP and RXN) via a 1:1 ratio transformer. The ADC samples
the incoming differential signal at a rate of 125M samples per second. Using a 64-level quanitizer it generates 6 digital
bits to represent each sample. The DSP adjusts the gain of the ADC according to the observed signal levels such that
the full dynamic range of the ADC can be used.
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DS00002267A-page 53