LAN9117 Datasheet, PDF (84/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
5.4.5 HASHL—MULTICAST HASH TABLE LOW REGISTER
Offset:
5
Attribute:
R/W
Default Value:
00000000h
Size:
32 bits
This register defines the lower 32-bits of the Multicast Hash Table. Please refer to Table 5.4.4, "HASHH—Multicast Hash
Table High Register" for further details.
Bits
31-0
Description
Lower 32 bits of the 64-bit Hash Table
5.4.6 MII_ACC—MII ACCESS REGISTER
Offset:
6
Attribute:
Default Value:
00000000h
Size:
This register is used to control the Management cycles to the PHY.
R/W
32 bits
Bits
31-16
15-11
10-6
5-2
1
0
Reserved
Description
PHY Address: Selects the external or internal PHY based on its address. The internal PHY is set to
address 00001b.
MII Register Index (MIIRINDA): These bits select the desired MII register in the PHY.
Reserved
MII Write (MIIWnR): Setting this bit tells the PHY that this will be a write operation using the MII data
register. If this bit is not set, this will be a read operation, packing the data in the MII data register.
MII Busy (MIIBZY): This bit must be polled to determine when the MII register access is complete.
This bit must read a logical 0 before writing to this register and MII data register.
The LAN driver software must set (1) this bit in order for the LAN9117 to read or write any of the MII
PHY registers.
During a MII register access, this bit will be set, signifying a read or write access is in progress. The
MII data register must be kept valid until the MAC clears this bit during a PHY write operation. The
MII data register is invalid until the MAC has cleared this bit during a PHY read operation.
DS00002267A-page 84
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