LAN9117 Datasheet, PDF (64/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
Bits
Description
9
TX Data FIFO Available Interrupt (TDFA_INT_EN)
8
TX Status FIFO Full Interrupt (TSFF_INT_EN)
7
TX Status FIFO Level Interrupt (TSFL_INT_EN)
6
RX Dropped Frame Interrupt Enable (RXDF_INT_EN)
5
Reserved
4
RX Status FIFO Full Interrupt (RSFF_INT_EN)
3
RX Status FIFO Level Interrupt (RSFL_INT_EN)
2-0 GPIO [2:0] (GPIOx_INT_EN).
Type
R/W
R/W
R/W
R/W
RO
R/W
R/W
R/W
5.3.5 BYTE_TEST—BYTE ORDER TEST REGISTER
Offset:
64h
Size:
32 bits
This register can be used to determine the byte ordering of the current configuration
Default
0
0
0
0
-
0
0
000
Bits
31:0 Byte Test
Description
Type
RO
Default
87654321h
5.3.6 FIFO_INT—FIFO LEVEL INTERRUPTS
Offset:
68h
Size:
32 bits
This register configures the limits where the FIFO Controllers will generate system interrupts.
Bits
31-24
23-16
15-8
Description
TX Data Available Level. The value in this field sets the level, in number of
64 Byte blocks, at which the TX FIFO Available interrupt (TFDA) will be
generated. When the TX data FIFO free space is greater than this value a
TX FIFO Available interrupt (TDFA) will be generated.
TX Status Level. The value in this field sets the level, in number of
DWORDs, at which the TX Status FIFO Level interrupt (TSFL) will be
generated. When the TX Status FIFO used space is greater than this value
an TX Status FIFO Level interrupt (TSFL) will be generated.
Reserved
7-0 RX Status Level. The value in this field sets the level, in number of
DWORDs, at which the RX Status FIFO Level interrupt (RSFL) will be
generated. When the RX Status FIFO used space is greater than this value
an RX Status FIFO Level interrupt (RSFL) will be generated.
Type
R/W
R/W
RO
R/W
Default
48h
00h
-
00h
DS00002267A-page 64
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