LAN9117 Datasheet, PDF (104/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
6.9 EEPROM Timing
The following specifies the EEPROM timing requirements for the LAN9117.
FIGURE 6-9:
EEPROM TIMING
TABLE 6-9: EEPROM TIMING VALUES
Symbol
Description
t_CKCYC
t_CKH
t_CKL
t_CSHCKH
t_CKLCSL
t_DVCKH
t_CKHDIS
t_DSCKH
t_DHCKH
t_CKLDIS
t_CSHDV
t_DHCSL
t_CSL
EECLK Cycle time
EECLK High time
EECLK Low time
EECS high before rising edge of EECLK
EECLK falling edge to EECS low
EEDIO valid before rising edge of EECLK
(OUTPUT)
EEDIO disable after rising edge EECLK
(OUTPUT)
EEDIO setup to rising edge of EECLK (INPUT)
EEDIO hold after rising edge of EECLK (INPUT)
EECLK low to data disable (OUTPUT)
EEDIO valid after EECS high (VERIFY)
EEDIO hold after EECS low (VERIFY)
EECS low
MIN
1110
550
550
1070
30
550
550
90
0
580
0
1070
TYP
MAX
1130
570
570
600
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS00002267A-page 104
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