LAN9117 Datasheet, PDF(31/114 Page) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

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LAN9117 Datasheet, PDF (31/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

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LAN9117

3.10.2.2 D2 Sleep

In this state, as shown in Table 3-9, all clocks to the MAC and host bus are disabled, and the PHY is placed in a reduced

power state. To enter this state, the EDPWRDOWN bit in register 17 of the PHY (Mode Control/Status register) must be

set. This places the PHY in the Energy Detect mode. The PM_MODE bits in the PMT_CTRL register must then be set

to 10b. Upon setting the PM_MODE bits, the LAN9117 will enter the D2 sleep state. The READY bit in PMT_CTRL is

cleared when entering the D2 state.

Note 3-9 If carrier is present when this state is entered detection will occur immediately.

If properly enabled via the ED_EN and PME_EN bits, LAN9117 will assert the PME hardware signal upon detection of

a valid carrier. Upon detection, the WUPS field in PMT_CTRL will be set to a 01b.

Note 3-10 The PME interrupt status bit on the INT_STS register (PME_INT) is set regardless of the setting of

PME_EN.

A write to the BYTE_TEST register, regardless of whether a carrier was detected, will return LAN9117 to the D0 state

and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check the READY bit and

verify that it is set before attempting any other reads or writes of the device. Before LAN9117 is fully awake from this

state the EDPWRDOWN bit in register 17 of the PHY must be cleared in order to wake the PHY. Do not attempt to clear

the EDPWRDOWN bit until the READY bit is set. After clearing the EDPWRDOWN bit the LAN9117 is ready to resume

normal operation. At this time the WUPS field can be cleared.

TABLE 3-9: POWER MANAGEMENT STATES

Device Block

(Normal Operation)

(WOL)

PHY

MAC Power

Management

MAC and Host Interface

Internal Clock

Full ON

RX Power Mgmt. Block On

OFF

Full ON

(Energy Detect)

Energy Detect Power-Down

OFF

Key

CLOCK ON

BLOCK DISABLED â CLOCK ON

FULL OFF

3.10.2.3 Power Management Event Indicators

Figure 3-11 is a simplified block diagram of the logic that controls the external PME, and internal pme_interrupt signals.

The pme_interrupt signal is used to set the PME_INT status bit in the INT_STS register, which, if enabled, will generate

a host interrupt upon detection of a power management event. The PME_INT status bit in INT_STS will remain set until

the internal pme_interrupt signal is cleared by clearing the WUPS bits, or by clearing the corresponding WOL_EN or

ED_EN bit. After clearing the internal pme_interrupt signal, the PME_INT status bit may be cleared by writing a â1â to

this bit in the INT_STS register. It should be noted that the LAN9117 can generate a host interrupt regardless of the state

of the PME_EN bit, or the external PME signal.

The external PME signal can be setup for pulsed, or static operation. When the PME_IND bit in the PMT_CTRL register

is set to a â1â, the external PME signal will be driven active for 50ms upon detection of a wake-up event. When the

PME_IND bit is cleared, the PME signal will be driven continuously upon detection of a wake-up event. The PME signal

is deactivated by clearing the WUPS bits, or by clearing the corresponding WOL_EN or ED_EN bit. The PME signal can

also be deactivated by clearing the PME_EN bit.

ï£ 2005-2016 Microchip Technology Inc.

DS00002267A-page 31

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