LAN9117 Datasheet, PDF (14/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
TABLE 2-6: MII INTERFACE SIGNALS (CONTINUED)
Pin No.
Name
30 Management Data
IO/External PHY
Detect
Symbol
MDIO
(EXT_PHY_DET)
Buffer
Type
I/O8 (PD)
# Pins
Description
1 Management Data IO: When
SMI_SEL = 1, this pin is the MII SMI
serial IO bus pin.
External PHY Detect: This pin also
functions as a strap input, which can
be used to indicate the presence of an
external PHY.
31 Management Data
Clock
MDC
O8 (PD)
See Note 2-2.
Note:
See Section 5.3.9,
"HW_CFG—Hardware
Configuration Register" for
more information on SMI_-
SEL and EXT_PHY_DET
1 Management Data Clock: When
SMI_SEL = 1, this pin is the MII
management data clock. When
SMI_SEL=0, this pin is driven low.
Note 2-2
See Note 2-2.
Note:
See Section 5.3.9,
"HW_CFG—Hardware
Configuration Register" for
more information on SMI_-
SEL.
The external SMI port is selected when SMI_SEL = 1. When SMI_SEL = 0, MDIO is tri-stated and
MDC is driven low.
DS00002267A-page 14
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