LAN9117 Datasheet, PDF (98/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS
and nRD are deasserted. They may be asserted and deasserted in any order.
6.3 PIO Burst Reads
In this mode, performance is improved by allowing up to 16, WORD read cycles back-to-back. PIO Burst Reads can be
performed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between
bursts for the period specified.
FIGURE 6-2:
LAN9117 PIO BURST READ CYCLE TIMING
A[7:5]
A[4:1]
nCS, nRD
Data Bus
Note: The “Data Bus” width is 16 bits.
TABLE 6-4:
Symbol
t_csh
t_csdv
t_acyc
t_asu
t_adv
t_ah
t_don
t_doff
t_doh
PIO BURST READ TIMING
Description
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Cycle Time
Address Setup to nCS, nRD valid
Address Stable to Data Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
MIN
TYP
MAX Units
13
ns
30
ns
45
0
ns
40
0
ns
0
ns
7
ns
0
ns
Note: A PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both
nCS and nRD are deasserted. They may be asserted and deasserted in any order.
DS00002267A-page 98
 2005-2016 Microchip Technology Inc.