LAN9117 Datasheet, PDF (69/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
TABLE 5-3: VALID TX/RX FIFO ALLOCATIONS (CONTINUED)
TX_FIF_SZ
TX Data FIFO Size TX Status FIFO Size RX Data FIFO Size RX Status FIFO Size
(Bytes)
(Bytes)
(Bytes)
(Bytes)
11
10752
512
4800
320
12
11776
512
3840
256
13
12800
512
2880
192
14
13824
512
1920
128
In addition to the host-accessible FIFOs, the MAC Interface Layer (MIL) contains an additional 2K bytes of TX, and 128
bytes of RX FIFO buffering. These sizes are fixed, and cannot be adjusted by the host.
As space in the TX MIL (Mac Interface Layer) FIFO frees, data is moved into it from the TX data FIFO. Depending on
the size of the frames to be transmitted, the MIL can hold up to two Ethernet frames. This is in addition to any TX data
that may be queued in the TX data FIFO.
Conversely, as data is received by the LAN9117, it is moved from the MAC to the RX MIL FIFO, and then into the RX
data FIFO. When the RX data FIFO fills up, data will continue to collect in the RX MIL FIFO. If the RX MIL FIFO fills up
and overruns, subsequent RX frames will be lost until room is made in the RX data FIFO. For each frame of data that
is lost, the RX Dropped Frames Counter (RX_DROP) is incremented.
RX and TX MIL FIFO levels are not visible to the host processor. RX and TX MIL FIFOs operate independent of the TX
adatand RX data and status FIFOs. FIFO levels set for the RX and TX data and Status FIFOs do not take into consid-
eration the MIL FIFOs.
5.3.10 RX_DP_CTRL—RECEIVE DATAPATH CONTROL REGISTER
Offset:
78h
This register is used to discard unwanted receive frames.
Size:
32 bits
Bits
31
30-0
Description
RX Data FIFO Fast Forward (RX_FFWD): Writing a ‘1’ to this bit causes
the RX data FIFO to fast-forward to the start of the next frame. This bit will
remain high until the RX data FIFO fast-forward operation has completed.
No reads should be issued to the RX data FIFO while this bit is high.
Note: Please refer to section “Receive Data FIFO Fast Forward” on
page 48 for detailed information regarding the use of RX_FFWD.
Reserved
Type
R/W
RO
Default
0h
-
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DS00002267A-page 69