LAN9117 Datasheet, PDF (30/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
3.10 Power Management
LAN9117 supports power-down modes to allow applications to minimize power consumption. The following sections
describe these modes.
3.10.1 SYSTEM DESCRIPTION
Power is reduced to various modules by disabling the clocks as outlined in Table 3-9, “Power Management States,” on
page 31. All configuration data is saved when in either of the two low power states. Register contents are not affected
unless specifically indicated in the register description.
3.10.2 FUNCTIONAL DESCRIPTION
There is one normal operating power state, D0 and there are two power saving states: D1, and D2. Upon entry into
either of the two power saving states, only the PMT_CTRL register is accessible for read operations. In either of the
power saving states the READY bit in the PMT_CTRL register will be cleared. Reads of any other addresses are for-
bidden until the READY bit is set. All writes, with the exception of the wakeup write to BYTE_TEST, are also forbidden
until the READY bit is set. Only when in the D0 (Normal) state, when the READY bit is set, can the rest of the device be
accessed.
Note 3-4
The LAN9117 must always be read at least once after power-up, reset, or upon return from a power-
saving state, otherwise write operations will not function.
In system configurations where the PME signal is shared amongst multiple devices, the WUPS field within the PMT_C-
TRL register can be read to determine which LAN9117 device is driving the PME signal.
When the LAN9117 is in a power saving state (D1 or D2), a write cycle to the BYTE_TEST register will return the
LAN9117 to the D0 state. Table 7-1, “Power Consumption Device Only,” on page 105 and Table 7-2, “Power Consump-
tion Device and System Components,” on page 106, shows the power consumption values for each power state.
Note 3-5
When the LAN9117 is in a power saving state, a write of any data to the BYTE_TEST register will
wake-up the device. DO NOT PERFORM WRITES TO OTHER ADDRRESSES while the READY bit
in the PMT_CTRL register is cleared.
3.10.2.1 D1 Sleep
Power consumption is reduced in this state by disabling clocks to portions of the internal logic as shown in Table 3-9. In
this mode the clock to the internal PHY and portions of the MAC are still operational. This state is entered when the host
writes a '01' to the PM_MODE bits in the Power Management (PMT_CTRL) register. The READY bit in PMT_CTRL is
cleared when entering the D1 state.
Wake-up frame and Magic Packet detection are automatically enabled in the D1 state. If properly enabled via the
WOL_EN and PME_EN bits, the LAN9117 will assert the PME hardware signal upon the detection of the wake-up frame
or magic packet. The LAN9117 can also assert the host interrupt (IRQ) on detection of a wake-up frame or magic packet.
Upon detection, the WUPS field in PMT_CTRL will be set to a 10b.
Note 3-6
The PME interrupt status bit (PME_INT) in the INT_STS register is set regardless of the setting of
PME_EN.
Note 3-7
Wake-up frame and Magic Packet detection is automatically enabled when entering the D1 state. For
wake-up frame detection, the wake-up frame filter must be programmed before entering the D1 state
(see Section 3.5, "Wake-up Frame Detection," on page 21). If used, the host interrupt and PME signal
must be enabled prior to entering the D1 state.
A write to the BYTE_TEST register, regardless of whether a wake-up frame or Magic Packet was detected, will return
LAN9117 to the D0 state and will reset the PM_MODE field to the D0 state. As noted above, the host is required to check
the READY bit and verify that it is set before attempting any other reads or writes of the device.
Note 3-8 The host must do only read accesses prior to the ready bit being set.
Once the READY bit is set, the LAN9117 is ready to resume normal operation. At this time the WUPS field can be
cleared.
DS00002267A-page 30
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