LAN9117 Datasheet, PDF (108/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
TABLE 7-5: 10BASE-T TRANSCEIVER CHARACTERISTICS
Parameter
Symbol
MIN
TYP MAX
Units
Notes
Transmitter Peak Differential Output
V_OUT
2.2
2.5
2.8
V
Voltage
Receiver Differential Squelch Threshold
V_DS
300
420
585
mV
Note 7-10
Note 7-10 Measured at the line side of the transformer, line replaced by 100 (+/- 1%) resistor.
7.6 Clock Circuit
The LAN9117 can accept either a 25MHz crystal (preferred) or a 25 MHz clock oscillator (50 PPM) input. The LAN9117
shares the 25MHz clock oscillator input (CLKIN) with the crystal input XTAL1 (pin 6). If the single-ended clock oscillator
method is implemented, XTAL2 should be left unconnected and CLKIN should be driven with a nominal 0-3.3V clock
signal. The input clock duty cycle is 40% minimum, 50% typical and 60% maximum.
It is recommended that a crystal utilizing matching parallel load capacitors be used for the LAN9117 crystal input/output
signals (XTAL1, XTAL2). See Table 7-6, "LAN9117 Crystal Specifications" for crystal specifications. Refer to Microchip
Application Note AN10.7 - “Parallel Crystal Circuit Input Voltage Control” and the LAN9117 Reference Schematic for
additional information.
TABLE 7-6: LAN9117 CRYSTAL SPECIFICATIONS
Parameter
Symbol
MIN
NOM
MAX
Crystal Cut
Crystal Oscillation Mode
Crystal Calibration Mode
Frequency
Frequency Tolerance @ 25^oC
Frequency Stability Over Temp
Frequency Deviation Over Time
Total Allowable PPM Budget
Shunt Capacitance
Load Capacitance
Drive Level
Equivalent Series Resistance
Operating Temperature Range
LAN9117 XTAL1 Pin Capacitance
LAN9117 XTAL2 Pin Capacitance
F_fund
F_tol
F_temp
F_age
C_O
C_L
P_W
R₁
AT, typ
Fundamental Mode
Parallel Resonant Mode
-
25.000
-
-
-
+/-50
-
-
+/-50
-
+/-3 to 5
-
-
-
+/-50
-
7 typ
-
-
20 typ
-
0.5
-
-
-
-
30
0
-
+70
-
3 typ
-
-
3 typ
-
Units
Notes
MHz
PPM
PPM
PPM
PPM
pF
pF
mW
Ohm
o_C
pF
pF
Note 7-11
Note 7-11
Note 7-12
Note 7-13
Note 7-14
Note 7-14
Note 7-11
Note 7-12
Note 7-13
Note 7-14
The maximum allowable values for Frequency Tolerance and Frequency Stability are application
dependent. Since any particular application must meet the IEEE +/-50 PPM Total PPM Budget, the
combination of these two values must be approximately +/-45 PPM (allowing for aging).
Frequency Deviation Over Time is also referred to as Aging.
The total deviation for the Transmitter Clock Frequency is specified by IEEE 802.3u as
+/- 50 PPM.
This number includes the pad, the bond wire and the lead frame. PCB capacitance is not included
in this value. The XTAL1 and XTAL2 pin and PCB capacitance values are required to accurately
calculate the value of the two external load capacitors. These two external load capacitors determine
the accuracy of the 25.000 MHz frequency.
DS00002267A-page 108
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