LAN9117 Datasheet, PDF (97/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
TABLE 6-2: READ AFTER READ TIMING RULES
After Reading...
Wait for this Many ns…
or Perform this Many Reads of
BYTE_TEST…
(Assuming Tcycle of 45ns)
RX Data FIFO
135
3
RX Status FIFO
135
3
TX Status FIFO
135
3
RX_DROP
180
4
Before Reading...
RX_FIFO_INF
RX_FIFO_INF
TX_FIFO_INF
RX_DROP
6.2 PIO Reads
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters in the CSRs are
latched at the beginning of the read cycle. Read data is valid as indicated in the timing diagram. PIO reads can be per-
formed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between
cycles for the period specified.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read cycles.
FIGURE 6-1:
LAN9117 PIO READ CYCLE TIMING
A[7:1]
nCS, nRD
Data Bus
Note: The “Data Bus” width is 16 bits.
TABLE 6-3:
Symbol
t_cycle
t_csl
t_csh
t_csdv
t_asu
t_ah
t_don
t_doff
t_doh
PIO READ TIMING
Description
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Setup to nCS, nRD Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
 2005-2016 Microchip Technology Inc.
MIN
TYP
MAX Units
45
ns
32
ns
13
ns
30
ns
0
ns
0
ns
0
ns
7
ns
0
ns
DS00002267A-page 97