LAN9117 Datasheet, PDF (23/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
Then the Function looks in the frame for 16 repetitions of the MAC address without any breaks or interruptions. In case
of a break in the 16 address repetitions, the PMT Function scans for the 48'hFF_FF_FF_FF_FF_FF pattern again in the
incoming frame.
The 16 repetitions may be anywhere in the frame but must be preceded by the synchronization stream. The device will
also accept a multicast frame, as long as it detects the 16 duplications of the MAC address. If the MAC address of a
node is 00h 11h 22h 33h 44h 55h, then the MAC scans for the following data sequence in an Ethernet: Frame.
Destination Address Source Address ……………FF FF FF FF FF FF
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55 00 11 22 33 44 55
…CRC
It should be noted that Magic Packet detection can be performed when LAN9117 is in the D0 or D1 power states. In the
D0 state, “Magic Packet” detection is enabled when the MPEN bit is set. In the D1 state, Magic Packet detection, as
well as wake-up frame detection, are automatically enabled when the device enters the D1 state.
3.6 Host Bus Operations
3.6.1 BUS WRITES
The host processor is required to perform two contiguous 16-bit writes to complete a single DWORD transfer. This
DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot change during a sixteen bit
write). No ordering requirements exist. The processor can access either the low or high word first, as long as the next
write is performed to the other word. If a write to the same word is performed, the LAN9117 disregards the transfer.
3.6.2 BUS READS
The host processor is required to perform two consecutive 16-bit reads to complete a single DWORD transfer. This
DWORD must begin and end on a DWORD address boundary (A[2] and higher, cannot change during a sixteen bit
read). No ordering requirements exist. The processor can access either the low or high word first, as long as the next
read is performed from the other word. If a read to the same word is performed, the data read is invalid and should be
re-read. This is not a fatal error. The LAN9117 will reset its read counters and restart a new cycle on the next read.
3.7 Big and Little Endian Support
The Microchip LAN9117 supports “Big-Endian” or “Little-Endian” processors with 16-bit bus interfaces. To support big-
endian processors, the hardware designer must explicitly invert the layout of the byte lanes. The WORD_SWAP—Word
Swap Control must be set correctly following Table 3-7, "Byte Lane Mapping".
Additionally, please refer to Section 5.3.17, "WORD_SWAP—Word Swap Control," on page 74 for additional informa-
tion on status indication on Endian modes.
TABLE 3-7: BYTE LANE MAPPING
Mode of Operation
Data Pins
D[15:8]
D[7:0]
Description
Mode 0 (WORD_SWAP—Word Swap Control equal to FFFFFFFFh)
A1 = 0
A1 = 1
Byte 3
Byte 1
Byte 2
Byte 0
Note: This mode can be used by 32-bit proces-
sors operating with an external 16-bit bus.
Mode 1 (WORD_SWAP—Word Swap Control not equal to FFFFFFFFh)
A1 = 0
A1 = 1
Byte 1
Byte 3
Byte 0
Byte 2
Note: This mode can also be used by native 16-
bit processors.
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