LAN9117 Datasheet, PDF (60/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
5.3 System Control and Status Registers
Table 5-1, "LAN9117 Direct Address Register Map", lists the registers that are directly addressable by the host bus.
TABLE 5-1: LAN9117 DIRECT ADDRESS REGISTER MAP
Control and Status Registers
Base Address +
Offset
50h
Symbol
ID_REV
Register Name
Chip ID and Revision.
54h
58h
5Ch
60h
64h
68h
6Ch
70h
74h
78h
7Ch
80h
84h
88h
8Ch
90h
94h
98h
9Ch
A0h
A4h
A8h
ACh
B0h
B4h
B8h - FCh
IRQ_CFG
INT_STS
INT_EN
RESERVED
BYTE_TEST
FIFO_INT
RX_CFG
TX_CFG
HW_CFG
RX_DP_CTL
RX_FIFO_INF
TX_FIFO_INF
PMT_CTRL
GPIO_CFG
GPT_CFG
GPT_CNT
RESERVED
WORD_SWAP
FREE_RUN
RX_DROP
MAC_CSR_CMD
MAC_CSR_DATA
AFC_CFG
E2P_CMD
E2P_DATA
RESERVED
Main Interrupt Configuration
Interrupt Status
Interrupt Enable Register
Reserved for future use
Read-only byte order testing register
FIFO Level Interrupts
Receive Configuration
Transmit Configuration
Hardware Configuration
RX Datapath Control
Receive FIFO Information
Transmit FIFO Information
Power Management Control
General Purpose IO Configuration
General Purpose Timer Configuration
General Purpose Timer Count
Reserved for future use
WORD SWAP Register
Free Run Counter
RX Dropped Frames Counter
MAC CSR Synchronizer Command (MAC
CSR’s are indexed through this register)
MAC CSR Synchronizer Data
Automatic Flow Control Configuration
EEPROM command (The EEPROM is
indexed through this register)
EEPROM Data
Reserved for future use
Default
See “ID_REV—
Chip ID and
Revision” on
page 61.
00000000h
00000000h
00000000h
-
87654321h
48000000h
00000000h
00000000h
00050000h
00000000h
00000000h
00001200h
00000000h
00000000h
0000FFFFh
0000FFFFh
-
00000000h
-
00000000h
00000000h
00000000h
00000000h
00000000h
00000000h
-
DS00002267A-page 60
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