LAN9117 Datasheet, PDF (73/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
Bits
Description
10:8 GPIO Direction 0-2 (GPDIRn). When set, enables the corresponding GPIO as
output. When cleared the GPIO is enabled as an input.
GPIO0 – bit 8
GPIO1 – bit 9
GPIO2 – bit 10
7:5 Reserved
4:3 GPO Data 3-4 (GPODn). The value written is reflected on GPOn.
GPO3 – bit 3
GPO4 – bit 4
2:0 GPIO Data 0-2 (GPIODn). When enabled as an output, the value written is
reflected on GPIOn. When read, GPIOn reflects the current state of the
corresponding GPIO pin.
GPIO0 – bit 0
GPIO1 – bit 1
GPIO2 – bit 2
Type
R/W
RO
R/W
R/W
Default
0000
-
00
000
TABLE 5-4: EEPROM ENABLE BIT DEFINITIONS
[22]
[21]
[20]
EEDIO Function
0
0
0
0
0
1
0
1
0
0
1
1
1
0
0
EEDIO
GPO3
GPO3
1
0
1
1
1
0
1
1
1
TX_EN
TX_EN
TX_CLK
Reserved
Reserved
EECLK Function
EECLK
GPO4
RX_DV
GPO4
RX_DV
RX_CLK
5.3.15 GPT_CFG-GENERAL PURPOSE TIMER CONFIGURATION REGISTER
Offset:
8Ch
Size:
32 bits
This register configures the General Purpose timer. The GP Timer can be configured to generate host interrupts at inter-
vals defined in this register.
Bits
31-30 Reserved
Description
Type
RO
Default
-
29 GP Timer Enable (TIMER_EN). When a one is written to this bit the GP
R/W
Timer is put into the run state. When cleared, the GP Timer is halted. On the
1 to 0 transition of this bit the GPT_LOAD field will be preset to FFFFh.
28-16 Reserved
RO
15-0 General Purpose Timer Pre-Load (GPT_LOAD). This value is pre-loaded R/W
into the GP-Timer.
0
-
FFFFh
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DS00002267A-page 73