LAN9117 Datasheet, PDF (29/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
WRAL (Write All): If erase/write operations are enabled in the EEPROM, this command will cause the contents of the
E2P_DATA register to be written to every EEPROM memory location. The EPC_TO bit is set if the EEPROM does not
respond within 30ms.
FIGURE 3-10:
EEPROM WRAL CYCLE
EECS
EECLK
EEDIO (OUTPUT)
EEDIO (INPUT)
1
0
0
0
1
t_CSL
D7
D0
Table 3-8, "Required EECLK Cycles", shown below, shows the number of EECLK cycles required for each EEPROM
operation.
TABLE 3-8:
REQUIRED EECLK CYCLES
Operation
ERASE
ERAL
EWDS
EWEN
READ
WRITE
WRAL
Required EECLK Cycles
10
10
10
10
18
18
18
3.9.2.2 MAC Address Reload
The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register. If a value of 0xA5h
is not found in the first address of the EEPROM, the EEPROM is assumed to be un-programmed and MAC Address
Reload operation will fail. The “MAC Address Loaded” bit indicates a successful load of the MAC address. The EPC_-
LOAD bit is set after a successful reload of the MAC address.
3.9.2.3 EEPROM Command and Data Registers
Refer to Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 77 and Section 5.3.24, "E2P_DATA –
EEPROM Data Register," on page 79 for a detailed description of these registers. Supported EEPROM operations are
described in these sections.
3.9.2.4 EEPROM Timing
Refer to Section 6.9, "EEPROM Timing," on page 104 for detailed EEPROM timing specifications.
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