LAN9117 Datasheet, PDF (9/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
TABLE 2-1:
Pin No.
43-46,49-
53,56-59,62-
64
12-18
92
93
94
72
76
HOST BUS INTERFACE SIGNALS
Name
Symbol
Buffer
Type
Host Data
D[15:0]
I/O8
Host Address
A[7:1]
IS
Read Strobe
nRD
IS
Write Strobe
nWR
IS
Chip Select
nCS
IS
Interrupt
Request
FIFO Select
IRQ
O8/OD8
FIFO_SEL
IS
# Pins
Description
16 Bi-directional data port.
7 7-bit Address Port. Used to select
Internal CSR’s and TX and RX FIFOs.
1 Active low strobe to indicate a read
cycle.
1 Active low strobe to indicate a write
cycle. This signal, qualified with nCS, is
also used to wakeup the LAN9117 when
it is in a reduced power state.
1 Active low signal used to qualify read
and write operations. This signal
qualified with nWR is also used to
wakeup the LAN9117 when it is in a
reduced power state.
1 Programmable Interrupt request.
Programmable polarity, source and
buffer types.
1 When driven high all accesses to the
LAN9117 are to the RX or TX Data
FIFOs. In this mode, the A[7:3] upper
address inputs are ignored.
TABLE 2-2: DEFAULT ETHERNET SETTINGS
Default Ethernet Settings
SPEED_SEL
Speed
Duplex
0
10MBPS
HALF-DUPLEX
1
100MBPS
HALF-DUPLEX
Auto Neg.
DISABLED
ENABLED
TABLE 2-3: LAN INTERFACE SIGNALS
Pin No.
Name
Symbol
79
TXP
TPO+
78
TXN
TPO-
83
RXP
TPI+
82
RXN
TPI-
87
PHY External Bias
EXRES1
Resistor
Buffer
Type
AO
AO
AI
AI
AI
# Pins
Description
1
Twisted Pair Transmit Output, Positive
1
Twisted Pair Transmit Output, Negative
1
Twisted Pair Receive Input, Positive
1
Twisted Pair Receive Input, Negative
1
Must be connected to ground through a
12.4K ohm 1% resistor.
 2005-2016 Microchip Technology Inc.
DS00002267A-page 9