LAN9117 Datasheet, PDF (101/114 Pages) SMSC Corporation – HIGH PERFORMANCE SINGLE-CHIP 10/100 NON-PCI ETHERNET CONTROLLER

LAN9117
6.6 PIO Writes
PIO writes are used for all LAN9117 write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable
(nWR). Either or both of these control signals must go high between cycles for the period specified.
FIGURE 6-6:
PIO WRITE CYCLE TIMING
A[7:1]
nCS, nWR
Data Bus
Note: The “Data Bus” width is 16 bits.
TABLE 6-6:
Symbol
t_cycle
t_csl
t_csh
t_asu
t_ah
t_dsu
t_dh
PIO WRITE CYCLE TIMING
Description
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
MIN
TYP
MAX Units
45
ns
32
ns
13
ns
0
ns
0
ns
7
ns
0
ns
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS
and nWR are deasserted. They may be asserted and deasserted in any order.
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DS00002267A-page 101