LAN9116 Datasheet, PDF (97/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
6.7 TX Data FIFO Direct PIO Writes
In this mode the upper address inputs are not decoded, and any write to the LAN9116 will write the TX Data FIFO. This
mode is enabled when FIFO_SEL is driven high during a write access. This is normally accomplished by connecting the
FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its address
when accessing the LAN9116. Timing is identical to a PIO write, and the FIFO_SEL signal has the same timing charac-
teristics as the address lines.
Timing for 16-bit and 32-bit cycles is identical with the exception that D[31:16] is ignored during a 16-bit write. Note that
address lines A[2:1] are still used when the LAN9116 is operating in 32-bit and 16-bit mode. Address bits A[7:3] are
ignored.
FIGURE 6-7:
TX DATA FIFO DIRECT PIO WRITE TIMING
FIFO_SEL
A[2:1]
nCS, nWR
Data Bus
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.
TABLE 6-7:
Symbol
t_cycle
t_csl
t_csh
t_asu
t_ah
t_dsu
t_dh
TX DATA FIFO DIRECT PIO WRITE TIMING
Description
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address, FIFO_SEL Setup to nCS, nWR Assertion
Address, FIFO_SEL Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
MIN
TYP
165
32
13
0
0
7
0
MAX
Units
ns
ns
ns
ns
ns
ns
ns
Note: A TX Data FIFO Direct PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends
when either or both nCS and nWR are deasserted. They may be asserted and deasserted in any order.
 2005-2016 Microchip Technology Inc.
DS00002268A-page 97