LAN9116 Datasheet, PDF (22/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
TABLE 3-7: BYTE LANE MAPPING
Mode of Operation
D[31:24]
Data Pins
D[23:16] D[15:8]
D[7:0]
Description
32-bit Byte 3
(MSB)
Byte 2
Byte 1
Byte 0
(LSB)
Mode 0 (WORD_SWAP—Word Swap Control equal to FFFFFFFFh)
This is the native mode of the LAN9116.
Endianess does not matter when both
WORD lanes are in operation.
A1 = 0
--
A1 = 1
--
--
Byte 3
Byte 2 Note: This mode can be used by 32-
--
Byte 1
Byte 0
bit processors operating with
an external 16-bit bus.
Mode 1 (WORD_SWAP—Word Swap Control not equal to FFFFFFFFh)
A1 = 0
--
--
Byte 1
Byte 0 Note:
A1 = 1
--
--
Byte 3
Byte 2
This mode can also be used by
native 16-bit processors.
Regarding the 32-bit mode description of operation comment described in the table above, mentioning “It should be
noted that Endianess does not matter when both WORD lanes are in operation” is true for the LAN9116 device. How-
ever, as in all designs, it is important for the PCB layout designer to route the signal byte lanes appropriately relative to
the processor type (Big vs. Little Endian).
3.8 General Purpose Timer (GP Timer)
The General Purpose Timer is a programmable block that can be used to generate periodic host interrupts. The reso-
lution of this timer is 100uS.
The GP Timer loads the GPT_CNT Register with the value in the GPT_LOAD field and begins counting down when the
TIMER_EN bit is set to a ‘1.’ On a reset, or when the TIMER_EN bit changes from set ‘1’ to cleared ‘0,’ the GPT_CNT
field is initialized to FFFFh. The GPT_CNT register is also initialized to FFFFh on a reset. Software can write the pre-
load value into the GPT_LOAD field at any time; e.g., before or after the TIMER_EN bit is asserted. The GPT Enable
bit TIMER_EN is located in the GPT_CFG register.
Once enabled, the GPT counts down either until it reaches 0000h or until a new pre-load value is written to the GPT_-
LOAD field. At 0000h, the counter wraps around to FFFFh, asserts the GPT interrupt status bit and the IRQ signal if the
GPT_INT_EN bit is set, and continues counting. The GPT interrupt status bit is in the INT_STS Register. The GPT_INT
hardware interrupt can only be set if the GPT_INT_EN bit is set. GPT_INT is a sticky bit (R/WC); i.e., once the GPT_INT
bit is set, it can only be cleared by writing a ‘1’ to the bit.
3.9 EEPROM Interface
LAN9116 can optionally load its MAC address from an external serial EEPROM. If a properly configured EEPROM is
detected by LAN9116 at power-up, hard reset or soft reset, the ADDRH and ADDRL registers will be loaded with the
contents of the EEPROM. If a properly configured EEPROM is not detected, it is the responsibility of the host LAN Driver
to set the IEEE addresses.
The LAN9116 EEPROM controller also allows the host system to read, write and erase the contents of the Serial
EEPROM. The EEPROM controller supports most “93C46” type EEPROMs configured for 128 x 8-bit operation.
3.9.1 MAC ADDRESS AUTO-LOAD
On power-up, hard reset or soft reset, the EEPROM controller attempts to read the first byte of data from the EEPROM
(address 00h). If the value A5h is read from the first address, then the EEPROM controller will assume that an external
Serial EEPROM is present. The EEPROM controller will then access the next EEPROM byte and send it to the MAC
Address register byte 0 (ADDRL[7:0]). This process will be repeated for the next five bytes of the MAC Address, thus
fully programming the 48-bit MAC address. Once all six bytes have been programmed, the “MAC Address Loaded” bit
is set in the E2P_CMD register. A detailed explanation of the EEPROM byte ordering with respect to the MAC address
is given in Section 5.4.3, "ADDRL—MAC Address Low Register," on page 77.
If an 0xA5h is not read from the first address, the EEPROM controller will end initialization. It is then the responsibility
of the host LAN driver software to set the IEEE address by writing to the MAC’s ADDRH and ADDRL registers.
DS00002268A-page 22
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