LAN9116 Datasheet, PDF (92/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
6.2 PIO Reads
PIO reads can be used to access CSRs or RX Data and RX/TX status FIFOs. In this mode, counters in the CSRs are
latched at the beginning of the read cycle. Read data is valid as indicated in the timing diagram. PIO reads can be per-
formed using Chip Select (nCS) or Read Enable (nRD). Either or both of these control signals must go high between
cycles for the period specified.
PIO reads are supported for both 16- and 32-bit access. Timing for 16-bit and 32-bit PIO Read cycles is identical with
the exception that D[31:16] are not driven during a 16-bit read.
Note: Some registers have restrictions on the timing of back-to-back, write-read and read-read cycles.
FIGURE 6-1:
LAN9116 PIO READ CYCLE TIMING
A[7:1]
nCS, nRD
Data Bus
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths
TABLE 6-3:
Symbol
t_cycle
t_csl
t_csh
t_csdv
t_asu
t_ah
t_don
t_doff
t_doh
PIO READ TIMING
Description
Read Cycle Time
nCS, nRD Assertion Time
nCS, nRD Deassertion Time
nCS, nRD Valid to Data Valid
Address Setup to nCS, nRD Valid
Address Hold Time
Data Buffer Turn On Time
Data Buffer Turn Off Time
Data Output Hold Time
MIN
TYP
165
32
13
0
0
0
0
MAX
30
7
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: A PIO Read cycle begins when both nCS and nRD are asserted. The cycle ends when either or both nCS
and nRD are deasserted. They may be asserted and deasserted in any order.
DS00002268A-page 92
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