LAN9116 Datasheet, PDF (68/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
5.3.16 GPT_CNT-GENERAL PURPOSE TIMER CURRENT COUNT REGISTER
Offset:
90h
This register reflects the current value of the GP Timer.
Size:
32 bits
Bits
31-16 Reserved
Description
15-0 General Purpose Timer Current Count (GPT_CNT). This 16-bit field
reflects the current value of the GP Timer.
Type
RO
RO
Default
-
FFFFh
5.3.17 WORD_SWAP—WORD SWAP CONTROL
Offset:
98h
Size:
32 bits
This register controls how words from the host data bus are mapped to the CRSs and Data FIFOs inside the LAN9116.
The LAN9116 always sends data from the Transmit Data FIFO to the network so that the low order word is sent first,
and always receives data from the network to the Receive Data FIFO so that the low order word is received first.
Bits
Description
Type
31:0 Word Swap. This field only has significance if the device is operated in 16- R/W
bit mode. In 32-bit mode, D[31:15] is always mapped to the high order word NASR
and D[15:0] is always mapped to the low order word. In 16-bit mode, if this
field is set to 00000000h, or anything except FFFFFFFFh, the LAN9116
maps words with address bit A[1]=1 to the high order words of the CSRs and
Data FIFOs, and words with address bit A[1]=0 to the low order words of the
CSRs and Data FIFOs. If this field is set to FFFFFFFFh, the LAN9116 maps
words with address bit A[1]=1 to the low order words of the CSRs and Data
FIFOs, and words with address bit A[1]=0 to the high order words of the
CSRs and Data FIFOs.
Note: Please refer to Section 3.6, "32-bit vs. 16-bit Host Bus Width Oper-
ation" for additional information.
Default
00000000h
5.3.18 FREE_RUN—FREE-RUN 25MHZ COUNTER
Offset:
9Ch
Size:
This register reflects the value of the free-running 25MHz counter.
32 bits
Bits
Description
31:0 Free Running SCLK Counter (FR_CNT):
Note:
This field reflects the value of a free-running 32-bit counter. At
reset the counter starts at zero and is incremented for every
25MHz cycle. When the maximum count has been reached the
counter will rollover. When read in 16-bit mode the count value is
latched on the first read.
• The FREE_RUN counter can take up to 160nS to clear after a reset
event.
• This counter will run regardless of the power management states D0, D1
or D2.
Type
RO
Default
-
DS00002268A-page 68
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