LAN9116 Datasheet, PDF(91/109 Page) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

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LAN9116 Datasheet, PDF (91/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

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LAN9116

TABLE 6-1: READ AFTER WRITE TIMING RULES (CONTINUED)

Minimum Wait Time for Read Following

Any Write Cycle

(in ns)

PMT_CTRL

330

GPIO_CFG

165

GPT_CFG

165

GPT_CNT

165

WORD_SWAP

165

FREE_RUN

330

RX_DROP

MAC_CSR_CMD

165

MAC_CSR_DATA

165

AFC_CFG

165

E2P_CMD

165

E2P_DATA

165

Number of BYTE_TEST Reads

(Assuming Tcycle of 165ns)

6.1.2 SPECIAL RESTRICTIONS ON BACK-TO-BACK READ CYCLES

There are also restrictions on specific back-to-back read operations. These restrictions concern reading specific regis-

ters after reading resources that have side effects. In many cases there is a delay between reading the LAN9116, and

the subsequent indication of the expected change in the control register values.

In order to prevent the host from reading stale data on back-to-back reads, minimum wait periods have been estab-

lished. These periods are specified in Table 6-2, "Read After Read Timing Rules". The host processor is required to wait

the specified period of time between read operations of specific combinations of resources. The wait period is depen-

dent upon the combination of registers being read.

Performing "dummy" reads of the BYTE_TEST register is a convenient way to ensure that the minimum wait time restric-

tion is met. Table 6-2 also shows the number of dummy reads that are required for back-to-back read operations. The

number of BYTE_TEST reads in this table is based on the minimum timing for Tcycle (165ns). For microprocessors with

slower busses the number of reads may be reduced as long as the total time is equal to, or greater than the time spec-

ified in the table. Dummy reads of the BYTE_TEST register are not required as long as the minimum time period is met.

TABLE 6-2: READ AFTER READ TIMING RULES

After Reading...

Wait for this Many nsâ¦

or Perform this Many Reads of

BYTE_TESTâ¦

(Assuming Tcyc of 165ns)

Before Reading...

RX Data FIFO

165

RX Status FIFO

165

TX Status FIFO

165

RX_DROP

330

RX_DP_CTRL

330

RX_FIFO_INF

TX_FIFO_INF

RX_DROP

TX Status FIFO

RX Status FIFO

Note 6-1

This restriction is only applicable after a fast-forward operation has been completed and the

RX_FFWD bit has been cleared. Refer to Section 3.13.1.1, "Receive Data FIFO Fast Forward," on

page 43 for more information.

ï£ 2005-2016 Microchip Technology Inc.

DS00002268A-page 91

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