LAN9116 Datasheet, PDF (64/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
5.3.11 RX_FIFO_INF—RECEIVE FIFO INFORMATION REGISTER
Offset:
7Ch
Size:
32 bits
This register contains the used space in the receive FIFOs of the LAN9116 Ethernet Controller.
Bits
31-24 Reserved
Description
23-16
15-0
RX Status FIFO Used Space (RXSUSED). Indicates the amount of space
in DWORDs, used in the RX Status FIFO.
RX Data FIFO Used Space (RXDUSED).). Reads the amount of space in
bytes, used in the RX data FIFO. For each receive frame, this field is
incremented by the length of the receive data rounded up to the nearest
DWORD (if the payload does not end on a DWORD boundary).
Type
RO
RO
RO
Default
-
00h
0000h
5.3.12 TX_FIFO_INF—TRANSMIT FIFO INFORMATION REGISTER
Offset:
80h
Size:
32 bits
This register contains the free space in the transmit data FIFO and the used space in the transmit status FIFO in the
LAN9116.
Bits
31-24 Reserved
Description
23-16
15-0
TX Status FIFO Used Space (TXSUSED). Indicates the amount of space in
DWORDS used in the TX Status FIFO.
TX Data FIFO Free Space (TDFREE). Reads the amount of space in bytes,
available in the TX data FIFO. The application should never write more data
than is available, as indicated by this value.
Type
RO
RO
RO
Default
-
00h
1200h
5.3.13 PMT_CTRL— POWER MANAGEMENT CONTROL REGISTER
Offset:
84h
Size:
32 bits
This register controls the Power Management features. This register can be read while the LAN9116 is in a power saving
mode.
Note: The LAN9116 must always be read at least once after power-up, reset, or upon return from a power-saving
state or write operations will not function.
DS00002268A-page 64
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