LAN9116 Datasheet, PDF (87/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
Bits
Description
1 Page Received.
1 = new page received
0 = new page not yet received
0 Link Partner Auto-Negotiation Able.
1 = link partner has auto-negotiation ability
0 = link partner does not have auto-negotiation ability
Type
RO/LH
RO
Default
0
0
5.5.8 MODE CONTROL/STATUS
Index (In Decimal):
17
Size:
16-bits
Bits
Description
15-14 Reserved. Write as 0; ignore on read.
13
12-2
EDPWRDOWN. Enable the Energy Detect Power-Down mode:
0=Energy Detect Power-Down is disabled
1=Energy Detect Power-Down is enabled
Reserved. Write as 0, ignore on read
1 ENERGYON. Indicates whether energy is detected This bit goes to a “0” if
no valid energy is detected within 256ms. Reset to “1” by hardware reset,
unaffected by SW reset.
0 Reserved. Write as “0”. Ignore on read.
Type
RW
RW
RW
RO
RW
Default
0
0
0
1
0
5.5.9 SPECIAL MODES
Index (In Decimal):
18
Size:
16-bits
Address
15-8 Reserved
Description
7:5
MODE: PHY Mode of operation. Refer to Table 5-9 for more details.
4:0
PHYAD: PHY Address:
The PHY Address is used for the SMI address.
Type
RW,
NASR
RW,
NASR
RW,
NASR
Default
See
Table 5-9
00001b
TABLE 5-9: MODE CONTROL
Mode
Mode Definitions
000
10Base-T Half Duplex. Auto-negotiation disabled.
001
10Base-T Full Duplex. Auto-negotiation disabled.
010
100Base-TX Half Duplex. Auto-negotiation disabled.
CRS is active during Transmit & Receive.
011
100Base-TX Full Duplex. Auto-negotiation disabled.
CRS is active during Receive.
Default Register Bit Values
Register 0
Register 4
[13,12,10,8]
0000
0001
1000
[8,7,6,5]
N/A
N/A
N/A
1001
N/A
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DS00002268A-page 87