LAN9116 Datasheet, PDF (32/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) within 2 ms. If
the software driver polls this bit and it is not set within 100ms, then an error condition
occurred.
3.11.4 SOFT RESET (SRST)
Soft reset is initiated by writing a ‘1’ to bit 0 of the HW_CFG register (SRST). This self-clearing bit will return to ‘0’ after
approximately 2 s, at which time the Soft Reset is complete. Soft reset does not clear control register bits marked as
NASR.
APPLICATION NOTE: Under normal conditions, the READY bit in PMT_CTRL will be set (high -”1”) immediately,
(within 2s). If the software driver polls this bit and it is not set within 100ms, then an error
condition occurred.
3.11.5 PHY RESET TIMING
The following sections and tables specify the operation and time required for the internal PHY to become operational
after various resets or when returning from the reduced power state.
3.11.5.1 PHY Soft Reset via PMT_CTRL bit 10 (PHY_RST)
The PHY soft reset is initiated by writing a ‘1’ to bit 10 of the PMT_CTRL register (PHY_RST). This self-clearing bit will
return to ‘0’ after approximately 100 s, at which time the PHY reset is complete.
3.11.5.2 PHY Soft Reset via PHY Basic Control Register (PHY Reg. 0.15)
The PHY Reg. 0.15 Soft Reset is initiated by writing a ‘1’ to bit 15 of the PHY’s Basic Control Register. This self-clearing
bit will return to ‘0’ at which time the PHY reset is complete.
3.12 TX Data Path Operation
Data is queued for transmission by writing it into the TX data FIFO. Each packet to be transmitted may be divided among
multiple buffers. Each buffer starts with a two DWORD TX command (TX command ‘A’ and TX command ‘B’). The TX
command instructs the LAN9116 on the handling of the associated buffer. Packet boundaries are delineated using con-
trol bits within the TX command.
The host provides a 16-bit Packet Tag field in the TX command. The Packet Tag value is appended to the corresponding
TX status DWORD. All Packet Tag fields must have the same value for all buffers in a given packet. If tags differ between
buffers in the same packet the TXE error will be asserted. Any value may be chosen for a Packet Tag as long as all tags
in the same Packet are identical. Packet Tags also provide a method of synchronization between transmitted packets
and their associated status. Software can use unique Packet Tags to assist with validating matching status completions.
Note 3-14 The use of packet tags is not required by the hardware. This is a software LAN driver only application
example for use of this field.
A Packet Length field in the TX command specifies the number of bytes in the associated packet. All Packet Length
fields must have the same value for all buffers in a given packet. Hardware compares the Packet Length field and the
actual amount of data received by the Ethernet controller. If the actual packet length count does not match the Packet
Length field as defined in the TX command, the Transmitter Error (TXE) flag is asserted.
The LAN9116 can be programmed to start payload transmission of a buffer on a byte boundary by setting the “Data Start
Offset” field in the TX command. The “Data Start Offset” field points to the actual start of the payload data within the first
8 DWORDs of the buffer. Data before the “Data Start Offset” pointer will be ignored. When a packet is split into multiple
buffers, each successive buffer may begin on any arbitrary byte.
The LAN9116 can be programmed to strip padding from the end of a transmit packet in the event that the end of the
packet does not align with the host burst boundary. This feature is necessary when the LAN9116 is operating in a system
that always performs multi-word bursts. In such cases the LAN9116 must ensure that it can accept data in multiples of
the Burst length regardless of the actual packet length. When configured to do so, the LAN9116 will accept extra data
at the end of the packet and will remove the extra padding before transmitting the packet. The LAN9116 automatically
removes data up to the boundary specified in the Buffer End Alignment field specified in each TX command.
The host can instruct the LAN9116 to issue an interrupt when the buffer has been fully loaded into the TX FIFO con-
tained in the LAN9116 and transmitted. This feature is enabled through the TX command ‘Interrupt on Completion’ field.
DS00002268A-page 32
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