LAN9116 Datasheet, PDF (61/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
5.3.8 TX_CFG—TRANSMIT CONFIGURATION REGISTER
Offset:
70h
Size:
This register controls the transmit functions on the LAN9116 Ethernet Controller.
32 bits
Bits
31-16 Reserved.
Description
15
14
13-3
Force TX Status Discard (TXS_DUMP). This self-clearing bit clears the TX
status FIFO of all pending status DWORD’s. When a ‘1’ is written, the TX
status pointers are cleared to zero.
Force TX Data Discard (TXD_DUMP). This self-clearing bit clears the TX
data FIFO of all pending data. When a ‘1’ is written, the TX data pointers are
cleared to zero.
Reserved
2 TX Status Allow Overrun (TXSAO). When this bit is cleared, data
transmission is suspended if the TX Status FIFO becomes full. Setting this
bit high allows the transmitter to continue operation with a full TX Status
FIFO.
Note: This bit does not affect the operation of the TX Status FIFO Full
interrupt.
1 Transmitter Enable (TX_ON). When this bit is set (1), the transmitter is
enabled. Any data in the TX FIFO will be sent. This bit is cleared
automatically when STOP_TX is set and the transmitter is halted.
0 Stop Transmitter (STOP_TX). When this bit is set (1), the transmitter will
finish the current frame, and will then stop transmitting. When the transmitter
has stopped this bit will clear. All writes to this bit are ignored while this bit
is high.
Type
RO
SC
SC
RO
R/W
R/W
SC
Default
-
0
0
-
0
0
0
5.3.9 HW_CFG—HARDWARE CONFIGURATION REGISTER
Offset:
74h
Size:
32 bits
This register controls the hardware configuration of the LAN9116 Ethernet Controller.
Note:
The transmitter and receiver must be stopped before writing to this register. Refer to Section 3.12.8, "Stop-
ping and Starting the Transmitter," on page 41 and Section 3.13.4, "Stopping and Starting the Receiver,"
on page 45 for details on stopping the transmitter and receiver.
Bits
31-21 Reserved
Description
20 Must Be One (MBO). This bit must be set to “1” for normal device operation.
16-19
TX FIFO Size (TX_FIF_SZ). Sets the size of the TX FIFOs in 1KB values to
a maximum of 14KB. The TX Status FIFO consumes 512 bytes of the space
allocated by TX_FIF_SIZ, and the TX data FIFO consumes the remaining
space specified by TX_FIF_SZ. The minimum size of the TX FIFOs is 2KB
(TX data and status combined). The TX data FIFO is used for both TX data
and TX commands.
The RX status and data FIFOs consume the remaining space, which is equal
to 16KB – TX_FIF_SIZ. See Section 5.3.9.1, "Allowable settings for
Configurable FIFO Memory Allocation," on page 62 for more information.
Type
RO
R/W
R/W
Default
-
0
5h
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DS00002268A-page 61