LAN9116 Datasheet, PDF (85/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
5.5.4 PHY IDENTIFIER 2
Index (In Decimal):
3
Size:
16-bits
Bits
Description
15-10 PHY ID Number b. Assigned to the 19th through 24th bits of the OUI.
9 - 4 Model Number. Six-bit manufacturer’s model number.
3 - 0 Revision Number. Four-bit manufacturer’s revision number.
Type
RO
RO
RO
Default
0xC0D1h
5.5.5 AUTO-NEGOTIATION ADVERTISEMENT
Index (In Decimal):
4
Size:
16-bits
Bits
15-14 Reserved
Description
13 Remote Fault. 1 = remote fault detected, 0 = no remote fault
12 Reserved
11-10
9
Pause Operation. (See Note 5-2)
00 No PAUSE
01 Symmetric PAUSE
10 Asymmetric PAUSE
11 Advertise support for both Symmetric PAUSE and Asymmetric PAUSE
Reserved
8 100Base-TX Full Duplex. 1 = TX with full duplex, 0 = no TX full duplex
ability
7 100Base-TX. 1 = TX able, 0 = no TX ability
6 10Base-T Full Duplex.
1 = 10Mbps with full duplex
0 = no 10Mbps with full duplex ability
5 10Base-T. 1 = 10Mbps able, 0 = no 10Mbps ability
4:0 Selector Field. [00001] = IEEE 802.3
Type
RO
R/W
R/W
R/W
RO
R/W
R/W
R/W
R/W
R/W
Default
00
0
0
00
0
See
Note 5-3
1
See
Note 5-3
See
Note 5-3
00001
Note 5-2
Note 5-3
When both symmetric PAUSE and asymmetric PAUSE support are advertised (value of 11), the
device will only be configured to, at most, one of the two settings upon auto-negotiation completion.
This default value of this bit is determined by Pin 74 "SPEED_SEL". Please refer to the pin
description section for more details.
 2005-2016 Microchip Technology Inc.
DS00002268A-page 85