LAN9116 Datasheet, PDF (96/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
6.6 PIO Writes
PIO writes are used for all LAN9116 write cycles. PIO writes can be performed using Chip Select (nCS) or Write Enable
(nWR). Either or both of these control signals must go high between cycles for the period specified.
PIO Writes are valid for 16- and 32-bit access. Timing for 16-bit and 32-bit PIO write cycles are identical with the excep-
tion that D[31:16] are ignored during a 16-bit write.
FIGURE 6-6:
PIO WRITE CYCLE TIMING
A[7:1]
nCS, nWR
Data Bus
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.
TABLE 6-6:
Symbol
t_cycle
t_csl
t_csh
t_asu
t_ah
t_dsu
t_dh
PIO WRITE CYCLE TIMING
Description
Write Cycle Time
nCS, nWR Assertion Time
nCS, nWR Deassertion Time
Address Setup to nCS, nWR Assertion
Address Hold Time
Data Setup to nCS, nWR Deassertion
Data Hold Time
MIN
TYP
165
32
13
0
0
7
0
MAX
Units
ns
ns
ns
ns
ns
ns
ns
Note: A PIO Write cycle begins when both nCS and nWR are asserted. The cycle ends when either or both nCS
and nWR are deasserted. They may be asserted and deasserted in any order.
DS00002268A-page 96
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