LAN9116 Datasheet, PDF(74/109 Page) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

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LAN9116 Datasheet, PDF (74/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

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LAN9116

Bits

Description

Type

9 EPC Time-out. If an EEPROM operation is performed, and there is no

R/WC

response from the EEPROM within 30mS, the EEPROM controller will time-

out and return to its idle state. This bit is set when a time-out occurs

indicating that the last operation was unsuccessful.

Note:

If the EEDIO signal pin is externally pulled-high, EPC commands

will not time out if the EEPROM device is missing. In this case the

EPC Busy bit will be cleared as soon as the command sequence

is complete. It should also be noted that the ERASE, ERAL,

WRITE and WRAL commands are the only EPC commands that

will time-out if an EEPROM device is not present -and- the EEDIO

signal is pulled low

8 MAC Address Loaded. When set, this bit indicates that a valid EEPROM RO

was found, and that the MAC address programming has completed normally.

This bit is set after a successful load of the MAC address after power-up, or

after a RELOAD command has completed

7-0 EPC Address. The 8-bit value in this field is used by the EEPROM

R/W

Controller to address the specific memory location in the Serial EEPROM.

This is a Byte aligned address.

Default

00h

5.3.24 E2P_DATA â EEPROM DATA REGISTER

Offset:

B4h

Size:

32 bits

This register is used in conjunction with the E2P_CMD register to perform read and write operations with the Serial

EEPROM

Bits

31-8 Reserved.

Description

7:0 EEPROM Data. Value read from or written to the EEPROM.

Type

R/W

Default

00h

5.4 MAC Control and Status Registers

These registers are located in the MAC module and are accessed indirectly through the MAC-CSR synchronizer port.

Table 5-6, "LAN9116 MAC CSR Register Map", shown below, lists the MAC registers that are accessible through the

indexing method using the MAC_CSR_CMD and MAC_CSR_DATA registers (see sections MAC_CSR_CMD â MAC

CSR Synchronizer Command Register and MAC_CSR_DATA â MAC CSR Synchronizer Data Register).

TABLE 5-6:

Index

LAN9116 MAC CSR REGISTER MAP

MAC Control and Status Registers

Symbol

MAC_CR

ADDRH

ADDRL

HASHH

HASHL

MII_ACC

MII_DATA

FLOW

MAC Control Register

MAC Address High

MAC Address Low

Multicast Hash Table High

Multicast Hash Table Low

MII Access

MII Data

Flow Control

Default

00040000h

0000FFFFh

FFFFFFFFh

00000000h

DS00002268A-page 74

ï£ 2005-2016 Microchip Technology Inc.

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