LAN9116 Datasheet, PDF (69/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
5.3.19 RX_DROP– RECEIVER DROPPED FRAMES COUNTER
Offset:
A0h
Size:
This register indicates the number of receive frames that have been dropped.
32 bits
Bits
31-0
Description
RX Dropped Frame Counter (RX_DFC). This counter is incremented every
time a receive frame is dropped. RX_DFC is cleared on any read of this
register.
An interrupt can be issued when this counter passes through its halfway
point (7FFFFFFFh to 80000000h).
Type
RC
Default
00000000h
5.3.20 MAC_CSR_CMD – MAC CSR SYNCHRONIZER COMMAND REGISTER
Offset:
A4h
Size:
32 bits
This register is used to control the read and write operations with the MAC CSR’s
Bits
31
30
29-8
Description
CSR Busy. When a 1 is written into this bit, the read or write operation is
performed to the specified MAC CSR. This bit will remain set until the
operation is complete. In the case of a read this means that the host can
read valid data from the data register. The MAC_CSR_CMD and
MAC_CSR_DATA registers should not be modified until this bit is cleared.
R/nW. When set, this bit indicates that the host is requesting a read
operation. When clear, the host is performing a write.
Reserved.
7-0 CSR Address. The 8-bit value in this field selects which MAC CSR will be
accessed with the read or write operation.
Type
SC
R/W
RO
R/W
Default
0
0
-
00h
5.3.21 MAC_CSR_DATA – MAC CSR SYNCHRONIZER DATA REGISTER
Offset:
A8h
Size:
32 bits
This register is used in conjunction with the MAC_CSR_CMD register to perform read and write operations with the MAC
CSR’s
Bits
Description
31-0 MAC CSR Data. Value read from or written to the MAC CSR’s.
Type
R/W
Default
00000000h
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DS00002268A-page 69