LAN9116 Datasheet, PDF (83/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
5.5 PHY Registers
The PHY registers are not memory mapped. These registers are accessed indirectly through the MAC via the MII_ACC
and MII_DATA registers. An index must be used to access individual PHY registers. PHY Register Indexes are shown
in Table 5-8, "LAN9116 PHY Control and Status Register"below.
Note: The NASR (Not Affected by Software Reset) designation is only applicable when bit 15 of the PHY Basic
Control Register (Reset) is set.
TABLE 5-8: LAN9116 PHY CONTROL AND STATUS REGISTER
PHY Control and Status Registers
Index
(In Decimal)
0
1
2
3
4
5
6
17
18
27
29
30
31
Register Name
Basic Control Register
Basic Status Register
PHY Identifier 1
PHY Identifier 2
Auto-Negotiation Advertisement Register
Auto-Negotiation Link Partner Ability Register
Auto-Negotiation Expansion Register
Mode Control/Status Register
Special Modes Register
Special Control/Status Indications
Interrupt Source Register
Interrupt Mask Register
PHY Special Control/Status Register
5.5.1 BASIC CONTROL REGISTER
Index (In Decimal):
0
Size:
16-bits
Bits
Description
Type
15 Reset. 1 = software reset. Bit is self-clearing. For best results, when setting RW/SC
this bit do not set other bits in this register.
14 Loopback. 1 = loopback mode, 0 = normal operation
RW
Default
0
0
13 Speed Select. 1 = 100Mbps, 0 = 10Mbps. Ignored if Auto Negotiation is
RW
enabled (0.12 = 1).
12 Auto-Negotiation Enable. 1 = enable auto-negotiate process (overrides
RW
0.13 and 0.8) 0 = disable auto-negotiate process.
11 Power Down. 1 = General power down-mode, 0 = normal operation.
RW
Note:
After this bit is cleared, the PHY may auto-negotiate with it's part-
ner station. This process may take a few seconds to complete.
Once auto-negotiation is complete, bit 5 of the PHY's Basic Status
Register will be set.
10 Reserved
RO
See Note 5-1
See Note 5-1
0
0
9 Restart Auto-Negotiate. 1 = restart auto-negotiate process 0 = normal
RW/SC
0
operation. Bit is self-clearing.
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DS00002268A-page 83