LAN9116 Datasheet, PDF (66/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
Bits
Description
Type
1 PME Enable (PME_EN). When set, this bit enables the external PME signal. R/W
This bit does not affect the PME interrupt (PME_INT).
0 Device Ready (READY). When set, this bit indicates that LAN9116 is ready
RO
to be accessed. This register can be read when LAN9116 is in any power
management mode. Upon waking from any power management mode,
including power-up, the host processor can interrogate this field as an
indication when LAN9116 has stabilized and is fully alive. Reads and writes of
any other address are invalid until this bit is set.
Note: With the exception of HW_CFG and PMT_CTRL, read access to
any internal resources is forbidden while the READY bit is cleared.
Default
0b
-
5.3.14 GPIO_CFG—GENERAL PURPOSE IO CONFIGURATION REGISTER
Offset:
88h
This register configures the GPIO and LED functions.
Size:
32 bits
Bits
31
30:28
27
26:24
23
22:20
19
18:16
15:11
10:8
Description
Reserved
LED[3:1] enable (LEDx_EN). A ‘1’ sets the associated pin as an LED output.
When cleared low, the pin functions as a GPIO signal.
LED1/GPIO0 – bit 28
LED2/GPIO1 – bit 29
LED3/GPIO2 – bit 30
Reserved
GPIO Interrupt Polarity 0-2 (GPIO_INT_POL). When set high, a high logic
level on the corresponding GPIO pin will set the corresponding INT_STS
register bit. When cleared low, a low logic level on the corresponding GPIO pin
will set the corresponding INT_STS register bit.
GPIO Interrupts must also be enabled in GPIOx_INT_EN in the INT_EN
register.
GPIO0 – bit 24
GPIO1 – bit 25
GPIO2 – bit 26
Note: GPIO inputs must be active for greater than 40nS to be recognized
as interrupt inputs.
Reserved
EEPROM Enable (EEPR_EN). The value of this field determines the function
of the external EEDIO and EECLK:
Please refer to Table 5-4 for the EEPROM Enable bit function definitions.
Note:
The host must not change the function of the EEDIO and EECLK
pins when an EEPROM read or write cycle is in progress. Do not use
reserved settings.
Reserved
GPIO Buffer Type 0-2 (GPIOBUFn). When set, the output buffer for the
corresponding GPIO signal is configured as a push/pull driver. When cleared,
the corresponding GPIO set configured as an open-drain driver.
GPIO0 – bit 16
GPIO1 – bit 17
GPIO2 – bit 18
Reserved
GPIO Direction 0-2 (GPDIRn). When set, enables the corresponding GPIO as
output. When cleared the GPIO is enabled as an input.
GPIO0 – bit 8
GPIO1 – bit 9
GPIO2 – bit 10
Type
RO
R/W
RO
R/W
RO
R/W
RO
R/W
RO
R/W
Default
-
000
-
000
-
000
-
000
-
0000
DS00002268A-page 66
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