LAN9116 Datasheet, PDF (95/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
6.5 RX Data FIFO Direct PIO Burst Reads
In this mode the upper address inputs are not decoded, and any burst read of the LAN9116 will read the RX Data FIFO.
This mode is enabled when FIFO_SEL is driven high during a read access. This is normally accomplished by connecting
the FIFO_SEL signal to a high-order address line. This mode is useful when the host processor must increment its
address when accessing the LAN9116. Timing is identical to a PIO Burst Read, and the FIFO_SEL signal has the same
timing characteristics as the address lines. In this mode, performance is improved by allowing an unlimited number of
back-to-back DWORD or WORD read cycles. RX Data FIFO Direct PIO Burst Reads can be performed using Chip
Select (nCS) or Read Enable (nRD). When either or both of these control signals go high, they must remain high for the
period specified.
Timing for 16-bit and 32-bit RX Data FIFO Direct PIO Burst Reads is identical with the exception that D[31:16] are not
driven during a 16-bit burst. Note that address lines A[2:1] are still used, and address bits A[7:3] are ignored.
FIGURE 6-4:
RX DATA FIFO DIRECT PIO BURST READ CYCLE TIMING
FIFO_SEL
A[2:1]
nCS, nRD
Data Bus
Note: The “Data Bus” width is 32 bits with optional support for 16-bit bus widths.
FIGURE 6-5:
RX DATA FIFO DIRECT PIO BURST READ CYCLE TIMING
Symbol
Description
MIN
TYP
t_csh
nCS, nRD Deassertion Time
13
t_csdv
nCS, nRD Valid to Data Valid
t_acyc
Address Cycle Time
165
t_asu
Address, FIFO_SEL Setup to nCS, nRD Valid
0
t_adv
Address Stable to Data Valid
t_ah
Address, FIFO_SEL Hold Time
0
t_don
Data Buffer Turn On Time
0
t_doff
Data Buffer Turn Off Time
t_doh
Data Output Hold Time
0
MAX
30
40
7
Units
ns
ns
ns
ns
ns
ns
ns
Note:
An RX Data FIFO Direct PIO Burst Read cycle begins when both nCS and nRD are asserted. The cycle
ends when either or both nCS and nRD are deasserted. They may be asserted and deasserted in any
order.
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DS00002268A-page 95