LAN9116 Datasheet, PDF (33/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
Upon completion of transmission, irrespective of success or failure, the status of the transmission is written to the TX
status FIFO. TX status is available to the host and may be read using PIO operations. An interrupt can be optionally
enabled by the host to indicate the availability of a programmable number TX status DWORDS.
Before writing the TX command and payload data to the TX FIFO, the host must check the available TX FIFO space by
performing a PIO read of the TX_FIFO_INF register. The host must ensure that it does not overfill the TX FIFO or the
TX Error (TXE) flag will be asserted.
The host proceeds to write the TX command by first writing TX command ‘A’, then TX command ‘B’. After writing the
command, the host can then move the payload data into the TX FIFO. TX status DWORD’s are stored in the TX status
FIFO to be read by the host at a later time upon completion of the data transmission onto the wire.
FIGURE 3-12:
SIMPLIFIED HOST TX FLOW DIAGRAM
init
Last Buffer in
Packet
Idle
Check
available
FIFO
space
TX Status
Available
Read TX
Status
(optional)
Write
TX
Command
Write
Start
Padding
(optional)
Write
Buffer
Not Last Buffer
3.12.1 TX BUFFER FORMAT
TX buffers exist in the host’s memory in a given format. The host writes a TX command word into the TX data buffer
before moving the Ethernet packet data. The TX command A and command B are 32-bit values that are used by the
LAN9116 in the handling and processing of the associated Ethernet packet data buffer. Buffer alignment, segmentation
and other packet processing parameters are included in the command structure. The following diagram illustrates the
buffer format.
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DS00002268A-page 33