LAN9116 Datasheet, PDF (81/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
Bits
Description
0
Flow Control Busy (FCBSY). This bit is set high whenever a pause frame or back pressure is being
transmitted. This bit should read logical 0 before writing to the Flow Control (FLOW) register. During
a transfer of Control Frame, this bit continues to be set, signifying that a frame transmission is in
progress. After the PAUSE control frame’s transmission is complete, the MAC resets to 0.
Note:
• When writing this register the FCBSY bit must always be zero.
• Applications must always write a zero to this bit
5.4.9 VLAN1—VLAN1 TAG REGISTER
Offset:
9
Attribute:
R/W
Default Value:
00000000h
Size:
32 bits
This register contains the VLAN tag field to identify VLAN1 frames. For VLAN frames the legal frame length is increased
from 1518 bytes to 1522 bytes.
Bits
31-16
15-0
Reserved
Description
VLAN1 Tag Identifier (VTI1). This contains the VLAN Tag field to identify the VLAN1 frames. This
field is compared with the 13th and 14th bytes of the incoming frames for VLAN1 frame detection.
If used, this register must be set to 0x8100.
5.4.10 VLAN2—VLAN2 TAG REGISTER
Offset:
A
Attribute:
R/W
Default Value:
00000000h
Size:
32 bits
This register contains the VLAN tag field to identify VLAN2 frames. For VLAN frames the legal frame length is increased
from 1518 bytes to 1522 bytes.
Bits
31-16
15-0
Reserved
Description
VLAN2 Tag Identifier (VTI2). This contains the VLAN Tag field to identify the VLAN2 frames. This
field is compared with the 13th and 14th bytes of the incoming frames for VLAN2 frame detection.If
used, this register must be set to 0x8100.
 2005-2016 Microchip Technology Inc.
DS00002268A-page 81