LAN9116 Datasheet, PDF (28/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
3.9.2.2 MAC Address Reload
The MAC address can be reloaded from the EEPROM via a host command to the E2P_CMD register. If a value of 0xA5h
is not found in the first address of the EEPROM, the EEPROM is assumed to be un-programmed and MAC Address
Reload operation will fail. The “MAC Address Loaded” bit indicates a successful load of the MAC address. The EPC_-
LOAD bit is set after a successful reload of the MAC address.
3.9.2.3 EEPROM Command and Data Registers
Refer to Section 5.3.23, "E2P_CMD – EEPROM Command Register," on page 72 and Section 5.3.24, "E2P_DATA –
EEPROM Data Register," on page 74 for a detailed description of these registers. Supported EEPROM operations are
described in these sections.
3.9.2.4 EEPROM Timing
Refer to Section 6.9, "EEPROM Timing," on page 99 for detailed EEPROM timing specifications.
3.10 Power Management
LAN9116 supports power-down modes to allow applications to minimize power consumption. The following sections
describe these modes.
3.10.1 SYSTEM DESCRIPTION
Power is reduced to various modules by disabling the clocks as outlined in Table 3-9, “Power Management States,” on
page 29. All configuration data is saved when in either of the two low power states. Register contents are not affected
unless specifically indicated in the register description.
3.10.2 FUNCTIONAL DESCRIPTION
There is one normal operating power state, D0 and there are two power saving states: D1, and D2. Upon entry into
either of the two power saving states, only the PMT_CTRL register is accessible for read operations. In either of the
power saving states the READY bit in the PMT_CTRL register will be cleared. Reads of any other addresses are for-
bidden until the READY bit is set. All writes, with the exception of the wakeup write to BYTE_TEST, are also forbidden
until the READY bit is set. Only when in the D0 (Normal) state, when the READY bit is set, can the rest of the device be
accessed.
Note 3-4
The LAN9116 must always be read at least once after power-up, reset, or upon return from a power-
saving state, otherwise write operations will not function.
In system configurations where the PME signal is shared amongst multiple devices, the WUPS field within the PMT_C-
TRL register can be read to determine which LAN9116 device is driving the PME signal.
When the LAN9116 is in a power saving state (D1 or D2), a write cycle to the BYTE_TEST register will return the
LAN9116 to the D0 state. Table 7-1, “Power Consumption Device Only,” on page 100 and Table 7-2, “Power Consump-
tion Device and System Components,” on page 101, shows the power consumption values for each power state.
Note 3-5
When the LAN9116 is in a power saving state, a write of any data to the BYTE_TEST register will
wake-up the device. DO NOT PERFORM WRITES TO OTHER ADDRRESSES while the READY bit
in the PMT_CTRL register is cleared.
3.10.2.1 D1 Sleep
Power consumption is reduced in this state by disabling clocks to portions of the internal logic as shown in Table 3-9. In
this mode the clock to the internal PHY and portions of the MAC are still operational. This state is entered when the host
writes a '01' to the PM_MODE bits in the Power Management (PMT_CTRL) register. The READY bit in PMT_CTRL is
cleared when entering the D1 state.
Wake-up frame and Magic Packet detection are automatically enabled in the D1 state. If properly enabled via the
WOL_EN and PME_EN bits, the LAN9116 will assert the PME hardware signal upon the detection of the wake-up frame
or magic packet. The LAN9116 can also assert the host interrupt (IRQ) on detection of a wake-up frame or magic packet.
Upon detection, the WUPS field in PMT_CTRL will be set to a 10b.
Note 3-6
The PME interrupt status bit (PME_INT) in the INT_STS register is set regardless of the setting of
PME_EN.
Note 3-7
Wake-up frame and Magic Packet detection is automatically enabled when entering the D1 state. For
wake-up frame detection, the wake-up frame filter must be programmed before entering the D1 state
DS00002268A-page 28
 2005-2016 Microchip Technology Inc.