LAN9116 Datasheet, PDF (24/109 Pages) SMSC Corporation – Highly Efficient Single-Chip 10/100 Non-PCI Ethernet Controller

LAN9116
FIGURE 3-3:
EEPROM ACCESS FLOW DIAGRAM
EEPROM Write
Idle
EEPROM Read
Idle
Write Data
Regis ter
W r ite
Command
Regis ter
Busy Bit = 0
Read
Command
Regis ter
Write
Command
Re gis te r
Read
Command
Re gis te r
Busy Bit = 0
Read Data
Re gis te r
The host can disable the EEPROM interface through the GPIO_CFG register. When the interface is disabled, the EEDIO
and ECLK signals can be used as general-purpose outputs, or they may be used to monitor internal MII signals.
3.9.2.1 Supported EEPROM Operations
The EEPROM controller supports the following EEPROM operations under host control via the E2P_CMD register. The
operations are commonly supported by “93C46” EEPROM devices. A description and functional timing diagram is pro-
vided below for each operation. Please refer to the E2P_CMD register description in Section 5.3.23, "E2P_CMD –
EEPROM Command Register," on page 72 for E2P_CMD field settings for each command.
ERASE (Erase Location): If erase/write operations are enabled in the EEPROM, this command will erase the location
selected by the EPC Address field (EPC_ADDR). The EPC_TO bit is set if the EEPROM does not respond within 30ms.
FIGURE 3-4:
EEPROM ERASE CYCLE
EECS
EECLK
EEDIO (OUTPUT)
EEDIO (INPUT)
1
1
1
A6
t_CSL
A0
DS00002268A-page 24
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