DS1035 Datasheet, PDF(76/106 Page) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

DS1035 Datasheet, PDF (76/106 Pages) Dallas Semiconductor – 3-in-1 High.Speed Silicon Delay Line

◁

DC and Switching Characteristics

MachXO2 Family Data Sheet

Switching Test Conditions

Figure 3-13 shows the output test load used for AC testing. The specific values for resistance, capacitance, volt-

age, and other test conditions are shown in Table 3-5.

Figure 3-13. Output Test Load, LVTTL and LVCMOS Standards

DUT

Test Poi nt

Table 3-5. Test Fixture Required Components, Non-Terminated Interfaces

Test Condition

Timing Ref.

LVTTL, LVCMOS 3.3 = 1.5V

LVCMOS 2.5 = VCCIO/2

LVTTL and LVCMOS settings (L -> H, H -> L)

ï¥

0pF LVCMOS 1.8 = VCCIO/2

LVCMOS 1.5 = VCCIO/2

LVCMOS 1.2 = VCCIO/2

LVTTL and LVCMOS 3.3 (Z -> H)

1.5

VOL

LVTTL and LVCMOS 3.3 (Z -> L)

1.5

VOH

Other LVCMOS (Z -> H)

188

0pF

VCCIO/2

VOL

Other LVCMOS (Z -> L)

VCCIO/2

VOH

LVTTL + LVCMOS (H -> Z)

VOH - 0.15

VOL

LVTTL + LVCMOS (L -> Z)

VOL - 0.15

VOH

Note: Output test conditions for all other interfaces are determined by the respective standards.

3-37

▷